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LX1562/1563
SECOND-GENERATION POWER FACTOR C O N T R O L L E R
T
HE
I
NFINITE
P
OWER
OF
I
N N O VAT I O N
P
RODUCTION
D
ATA
S
HEET
DESCRIPTION The LX1562 is a second-generation family of power factor correction controllers using a discontinuous mode of operation. They are optimized for electronic ballast applications. Many improvements have been made over the original SG3561A controller introduced by Silicon General Semiconductor in 1992. New features include the addition of an internal start-up circuit eliminating bulky external components while allowing independent boost converter operation. Addition of internal current sense blanking eliminating the need for an external R/C filter network. Internal clamping of the error amplifier and multiplier outputs improves turn on overshoot characteristics and current limiting. Special circuitry has also been added to prevent no load runaway conditions. And finally, output drive clamps limiting power MOSFET gate drive independent of supply voltage greatly enhance the products practical application. Although the IC design has been optimized for electronic ballast applications, it can also be used for power factor correction in lower power (typ < 300W) AC-DC converters. One unique feature of the device is encompassed by the addition of internal logic circuitry to detect zero crossing of the inductor current thus maintaining the discontinuous current mode of operation. This feature prevents large current gaps from appearing thereby minimizing distortion and enhancing power factor correction.
K E Y F E AT U R E S
s INTERNAL START-UP CIRCUIT s INTERNAL CURRENT SENSE BLANKING s IMPROVED MICROPOWER START-UP CURRENT (300A max.) s CLAMPED E.A. OUTPUT FOR LOWER TURN-ON OVERSHOOT s MULTIPLIER CLAMP LIMITS MAXIMUM INPUT CURRENT s INTERNAL OVERVOLTAGE PROTECTION REPLACES BUILT-IN C.S. OFFSET s PWM OUTPUT CLAMP LIMITS MOSFET GATE DRIVE VOLTAGE s INCREASED UVLO HYSTERESIS REDUCES START-UP TIMING (LX1562 only) s LOW OPERATING CURRENT CONSUMPTION s INTERNAL 1.5% REFERENCE s TOTEM POLE OUTPUT STAGE s AUTOMATIC CURRENT LIMITING OF BOOST STAGE s DISCONTINUOUS MODE OF OPERATION WITH NO CURRENT GAPS s NO SLOPE COMPENSATION REQUIRED
PRODUCT HIGHLIGHT
TYPICAL APPLICATION OF THE LX1562 IN AN 80W FLUORESCENT LAMP BALLAST WITH ACTIVE POWER FACTOR CONTROL
450H 61T #22AWG 100k 1/2W L1 R3 7T D5 R4 22k 1N4935
8 VIN 5 I DET OUT 7
A P P L I C AT I O N S
s ELECTRONIC BALLAST s SWITCHING POWER SUPPLIES
MR854 D7
VBOOST 230V
D1
D3
1N4004
1N4004
AC+ EMI FILTER 120V AC AC-
R1 C1 1F 250V
2.2M 1%
C2 22F R10 4.7M
R7
FLOURESCENT LAMP BALLAST
D6 1N4148 47 R5 R9 620k C5 0.1F
1M 1%
Q1 1RF730
A VA I L A B L E O P T I O N S
Part # LX1562 LX1563 Start-Up Voltage 13.1V 9.8V
PER
PA R T #
Hysteresis Voltage 5.2V 2.1V
LX1562
3
MULT IN
D2
D4
COMP INV
2 1 4
C6 100F 400V 11k 1% R6 1.3 R8
R2
1N4004
1N4004
0.1F
29k 1%
C3 C4 .01F
GND 6
C.S.
3x 1/4W
Note: Thick trace on schematic shows high-frequency, high-current path in circuit. Lead lengths must be minimized to avoid high-frequency noise problems.
PA C K A G E O R D E R I N F O R M AT I O N TA (C) 0 to 100 0 to 100
M Plastic DIP 8-pin
LX1562IM LX1563IM
DM Plastic SOIC 8-pin
LX1562IDM LX1563IDM
Note: All surface-mount packages are available in Tape & Reel. Append the letter "T" to part number. (i.e. LX1562IDMT)
F O R F U R T H E R I N F O R M AT I O N C A L L ( 7 1 4 ) 8 9 8 - 8 1 2 1
Copyright (c) 1996 Rev. 1.3 12/96
11861 WESTERN AVENUE, GARDEN GROVE, CA. 92841
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PRODUCT DATABOOK 1996/1997
LX1562/1563
SECOND-GENERATION POWER FACTOR C O N T R O L L E R
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D
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A B S O L U T E M A X I M U M R AT I N G S
(Note 1)
PACKAGE PIN OUTS
E.A. INV. E.A. OUT MULT. INPUT C.S.
1 2 3 4 8 7 6 5
Supply Voltage (VIN) ...................................................................................... -0.3V to 28V Peak Driver Output Current (Note 3) ................................................................. 500mA Driver Output Clamping Diodes VO > VCC or VO < -0.3V ........................................................................................ 10mA Detector Clamping Diodes VDET > 6V or VDET < 0.9V ..................................................................................... 10mA Error Amp, Multiplier, and Comparator Input Voltages ................................ -0.3V to 6V Detector Input Voltage (Note 2) ....................................................................... -0.3 to 6V Operating Junction Temperature Plastic (M and DM Packages) ............................................................................... 150C Storage Temperature Range ...................................................................... -65C to 150C Lead Temperature (Soldering, 10 Seconds) ............................................................ 300C
Note 1. Values beyond which damage may occur. All voltages are specified with respect to ground, and all currents are positive into the specified terminal. Note 2. With no limiting resistor. Note 3. Current duty cycle is chosen such that TJ is below 150C.
VIN OUT GROUND IDET
M PACKAGE (Top View)
E.A. INV. E.A. OUT MULT. INPUT C.S.
1 2 3 4
8 7 6 5
VIN OUT GROUND IDET
DM PACKAGE (Top View)
T H E R M A L D ATA
M PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, JA DM PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, JA 165C/W 95C/W
Junction Temperature Calculation: TJ = TA + (PD x JA). The JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow
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Copyright (c) 1996 Rev. 1.3 12/96
PRODUCT DATABOOK 1996/1997
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SECOND-GENERATION POWER FACTOR C O N T R O L L E R
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R E C O M M E N D E D O P E R AT I N G C O N D I T I O N S Parameter
Supply Voltage Range Peak Driver Output Current Operating Ambient Temperature Range: LX1562/1563 Note 4. Range over which the device is functional.
(Note 4)
Symbol
Recommended Operating Conditions Min. Typ. Max.
11 200 0 100 25
Units
V mA C
ELECTRICAL
CHARACTERISTICS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for the LX1562/1563 with 0C TA 100C; VIN=12V. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter Under-Voltage Lockout Section
Start Threshold Voltage UV Lockout Hysteresis
Symbol
Test Conditions
LX1562I/1563I Min. Typ. Max.
12 9.2 4 1.7 13.1 9.8 5.2 2.1 200 5 6 2.465 2.44 2.50 0.1 1.3 20 -500 60 60 -2 3 1.2 50 80 0.63 80 -4.5 4.5 1.7 49 0 V REF 2 VREF + 1 -0.24 0.68 0.61 -0.2 1.24 0.8 0.75 1.45 500 14 10.6 6 2.5 300 8 10 2.535 2.56
Units
VST VH
LX1562 Only LX1563 Only LX1562 Only LX1563 Only VIN < V TH VIN = 12V, Output Not Switching VIN = 12V, 50kHz, CGS = 1000pF IREF = 0mA, TA = 25C IREF = 0mA 12V < VIN < 25V 0 < IREF < 2mA
V V V V A mA mA V V mV mV mV nA dB V/sec dB mA mA V MHz V V A V/V2 V/V2 %/C V
Supply Current Section
Start-Up Supply Current Operating Supply Current Dynamic Operating Supply Current IST IQ IOP VR VI VL VT IB AVOL S PSRR I SR ISK E.A.O fB B VM1 VM2 IMB K KT V CLMP
Reference Section (Note 5)
Initial Accuracy (Note 8) Line Regulation Load Regulation Temperature Stability
Error Amplifier Section
Input Bias Current Large Signal Open Loop Voltage Gain Slew Rate Power Supply Rejection Ratio (Note 5) Output Source Current Output Sink Current Output Voltage Range (Note 7) Unity Gain Bandwidth Phase Margin (Note 5) 11 to 25V VOH = 3V VOL = 2V No Load on E.A. Output
3.8
Multiplier Section
Mult. Input Voltage Range M2 Input Voltage Range Mult. Input Bias Current (M1) Multiplier Gain (Note 5 & 6) Multiplier Gain Temperature Stability Maximum Multiplier Output Voltage
VM1 = 1V, VEA0 = 2.7V to 3.3V VM1 = 0.5V to 1.5V, VEA0 = VREF + 1V VM1 = 2V, VPIN1 = 0V
0.55 0.55 1.1
( E l e c tr i c a l Cha r a ct er i st i cs cont i nu e next pa g e.)
Copyright (c) 1996 Rev. 1.3 12/96
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SECOND-GENERATION POWER FACTOR C O N T R O L L E R
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ELECTRICAL CHARACTERISTICS Parameter Symbol Test Conditions
0V VCS 1.7V E.A.OUT = 3.7V, VCS = 0 to 1.2V, VM1 = 1V VEA0 = 2.2V, VM1 = 0V, IDETC = 0V
(Con't.)
LX1562I/1563I Min. Typ. Max.
-1 0.4 -20 1.6 180 0.4 7.0 -1 -0.3 280 0.9 3 1.72 240 0.62 7.8 -0.2 1 500 1.2 20 1.9 300 0.85 8.6 1 3
Units
Current Sense Comparator Section
Input Bias Current Current Sense Delay to Output C.S. Blanking Time C.S. Input Offset Voltage I CSB td tBLK VOFF VHI HD VDL VDZ IDB IDMX tRST V PRH V PRL tR tf VDRMX IL = -10mA, VIN = 12V IL = 10mA, VIN = 12V CL = 1000pF CL = 1000pF VIN = 20V 8.5 A ns s mV V mV V V A mA sec V V ns ns V
Detect Section
Input Voltage Threshold - High Hysteresis Input LO Clamp Voltage Input HI Clamp Voltage Input Current Input HI/LO Clamp Diode Current
IDET = 100A IDET = 3mA 1V VDET 6V VDET < 0.9V, VDET > 6V
Restart Timer Section
Restart Time 300 9 0.8 130 50 13.8
Output Driver Section
Output High Voltage Output Low Voltage Output Rise Time Output Fall Time Maximum Output Voltage 1 200 120 15
13
Notes: 5. Because the reference is not brought out externally, these specifications are tested at probe only, and cannot be tested on the packaged part. They are guaranteed by design, and shown for illustrative purposes only. 6. K = VC.S. (VM1) x (VEA0 - VREF) VC.S. (VM1) (VEA0)
7. This parameter, although guaranteed, is not tested in production. 8. Initial accuracy includes input offset voltage of error amplifier.
4
Copyright (c) 1996 Rev. 1.3 12/96
PRODUCT DATABOOK 1996/1997
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SECOND-GENERATION POWER FACTOR C O N T R O L L E R
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BLOCK DIAGRAM / PIN DESCRIPTIONS
EMI Filter C1
VIN
8
5.2V (1562) 2.1V (1563)
Internal Bias
2.5V REF
AC Input VREF
L1
VREF 6.8V To All Internal Circuitry
L1
D1
MULT IN
3
13.1V (1562) 9.8V (1563) 1.24V
M1 M2
E.A. INV.
1
2
UVLO
E.A. OUT
C.S. 1.8V LATCH Q
VIN
OUT
7
R VREF
IDET 300
5
L1 S 1.72V VTIMER Q C.S.
C.S.
4
1s Delay
FUNCTIONAL DESCRIPTION Pin
VIN GND INV E.A. OUT MULT IN C.S.
#
8 6 1 2 3 4
Description
Input supply voltage. Input supply voltage return. Must always be the lowest potential of all the pins. Inverting input of the Error Amplifier. The output of the Boost converter should be resistively divided to 2.5V and connected to this pin. The output of the Error Amplifier. A feedback compensation network is placed between this pin and the INV pin. Input to the multiplier stage. The full-wave rectified AC is divided to less than 2V and is connected to this pin. Input to the PWM comparator. Current is sensed in the Boost stage MOSFET by a resistor in the source lead, and is fed to this pin. An internal blanking circuit eliminates the RC low pass filter that otherwise is required to eliminate leading edge spike. A current driven logic input with internal clamp. A second winding on the Boost inductor senses the flyback voltage associated with the zero crossing of the inductor current and feeds it to the IDET pin through a limiting resistor. Low on this pin causes V O (pin 7) to go high. PWM output pin. A totem-pole output stage specially designed for direct driving the MOSFET.
I DET
5
OUT
7
Copyright (c) 1996 Rev. 1.3 12/96
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PRODUCT DATABOOK 1996/1997
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GRAPH / CURVE INDEX
FIGURE INDEX
Characteristic Curves
FIGURE # 1. 2. 3. 4. 5. 6. 7. 8. 9. E.A. OUTPUT VOLTAGE vs. C.S. THRESHOLD MULTIPLIER INPUT VOLTAGE vs. C.S. THRESHOLD MULTIPLIER GAIN (VM1=1V, VEA0 =3.5V) vs. TEMPERATURE REFERENCE VOLTAGE (Including Offset) vs. TEMPERATURE E.A. INPUT BIAS CURRENT vs. TEMPERATURE E.A. SINK CURRENT @2V vs. TEMPERATURE START-UP SUPPLY CURRENT vs. TEMPERATURE (LX1563) START-UP SUPPLY CURRENT vs. TEMPERATURE (LX1562) START-UP THRESHOLD vs. TEMPERATURE (LX1562) FIGURE # 23. INDUCT CURRENT
IC Description
24. TYPICAL APPLICATION OF START-UP CIRCUITRY 25. START-UP CAPACITOR VOLTAGE 26. VOLTAGE REFERENCE vs. TEMPERATURE 27. THE AMPLIFIER CONFIGURED AS AN INTEGRATOR FOR LOOP COMPENSATION 28. MULTIPLIER SECTION 29. CURRENT SENSE SECTION 30. START-UP TIMER
10. START-UP THRESHOLD vs. TEMPERATURE (LX1563) 11. UV LOCKOUT HYSTERESIS vs. TEMPERATURE (LX1562) 12. UV LOCKOUT HYSTERESIS vs. TEMPERATURE (LX1563) 13. IDET THRESHOLD HIGH vs. TEMPERATURE 14. IDET INPUT HYSTERESIS vs. TEMPERATURE 15. RUN-AWAY COMPARATOR THRESHOLD vs. TEMPERATURE 16. C.S. DELAY TO OUTPUT vs. TEMPERATURE 17. C.S. BLANKING TIME vs. TEMPERATURE 18. RESTART TIME vs. TEMPERATURE 19. FALL TIME vs. TEMPERATURE 20. RISE TIME vs. TEMPERATURE 21. SUPPLY CURRENT vs. SUPPLY VOLTAGE (LX1562) 22. SUPPLY CURRENT vs. SUPPLY VOLTAGE (LX1563) 22a. MAXIMUM MULTIPLIER OUTPUT VOLTAGE vs. TEMPERATURE FIGURE # 36. TYPICAL APPLICATION OF THE LX1562 IN AN 80W FLUORESCENT LAMP BALLAST WITH ACTIVE POWER FACTOR CONTROL - 120V 37. TYPICAL APPLICATION OF THE LX1562 IN AN 80W FLUORESCENT LAMP BALLAST WITH ACTIVE POWER FACTOR CONTROL - 220V 38. TYPICAL APPLICATION OF THE LX1562 IN AN 80W FLUORESCENT LAMP BALLAST WITH ACTIVE POWER FACTOR CONTROL - 277V FIGURE # 31. TYPICAL APPLICATION OF THE LX1562 IN AN 80W FLUORESCENT LAMP BALLAST WITH ACTIVE POWER FACTOR CONTROL 32. NORMALIZED OPERATING FREQUENCY vs. OFF-TIME DUTY CYCLE 33. INDUCT CURRENT 34. LOAD TRANSIENT RESPONSE CIRCUIT 35. FLYBACK VOLTAGE ACROSS IDET WINDING
Application Information
Typical Applications
6
Copyright (c) 1996 Rev. 1.3 12/96
PRODUCT DATABOOK 1996/1997
LX1562/1563
SECOND-GENERATION POWER FACTOR C O N T R O L L E R
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CHARACTERISTIC
C U RV E S
FIGURE 1. -- E.A. OUTPUT VOLTAGE vs. C.S. THRESHOLD
1.4
FIGURE 2. -- MULTIPLIER INPUT VOLTAGE vs. C.S. THRESHOLD
1.4
VM1 = 3V
1.2
1.2
VEA0 = 4V
TA = 25C
C.S. Threshold Voltage - (V)
VM1 = 2.5V
VEA0 = 3.5V
1.0
C.S. Threshold - (V)
1.0
0.8
0.8
VEA0 = 3V
0.6
0.6
VM1 = 1V VM1 = 1.5V VM1 = 2V TA = 25C
VEA0 = 3.25V
0.4
0.4 0.2
VEA0 = 2.5V
0.2
0 2.4
0
2.6
2.8
3
3.2
3.4
3.6
3.8
4
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
E.A. Output Voltage - (V)
Multiplier Input Voltage - (V)
FIGURE 3. -- MULTIPLIER GAIN (VM1=1V, VEA0 =3.5V)
vs. TEMPERATURE
0.80
FIGURE 4. -- REFERENCE VOLTAGE (Including Offset)
vs. TEMPERATURE
2.52
(VR) Reference Voltage - (V)
0.75
(K) Multiplier Gain - (1/V)
VCC = 12V CL = 1nF VEA0 = 3.5V VM1 = 1V
2.51 2.50 2.49
VCC = 12V CL = 1nF
0.70
0.65
2.48 2.47
0.60
0.55
2.46 2.45 -50
0.50 -50
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
(TA) Ambient Temperature - (C)
(TA) Ambient Temperature - (C)
Copyright (c) 1996 Rev. 1.3 12/96
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PRODUCT DATABOOK 1996/1997
LX1562/1563
SECOND-GENERATION POWER FACTOR C O N T R O L L E R
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D
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CHARACTERISTIC
C U RV E S
FIGURE 5. -- E.A. INPUT BIAS CURRENT vs. TEMPERATURE
0.5 0.4
FIGURE 6. -- E.A. SINK CURRENT @2V vs. TEMPERATURE
6.0
(ISK) E.A. Sink Current @2V - (mA)
(IB) E.A. Input Bias Current - (A)
0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -50
VCC = 12V CL = 1nF E.A.- = 2.5V
5.5
VCC = 12V CL = 1nF VEA0 = 2V
5.0
4.5
4.0
3.5
-25
0
25
50
75
100
125
3.0 -50
-25
0
25
50
75
100
125
(TA) Ambient Temperature - (C)
(TA) Ambient Temperature - (C)
FIGURE 7. -- START-UP SUPPLY CURRENT vs. TEMPERATURE
350.0
FIGURE 8. -- START-UP SUPPLY CURRENT vs. TEMPERATURE
350.0
LX1563
LX1562
(IST) Start-up Supply Current - (A)
(IST) Start-up Supply Current - (A)
300.0 250.0 200.0
VIN < VTH CL = 1nF
300.0 250.0 200.0
VIN < VTH CL = 1nF
150.0 100.0
150.0 100.0
50.0 0.0 -50
50.0 0.0 -50
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
(TA) Ambient Temperature - (C)
(TA) Ambient Temperature - (C)
8
Copyright (c) 1996 Rev. 1.3 12/96
PRODUCT DATABOOK 1996/1997
LX1562/1563
SECOND-GENERATION POWER FACTOR C O N T R O L L E R
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CHARACTERISTIC
C U RV E S
FIGURE 9. -- START-UP THRESHOLD vs. TEMPERATURE
14.0
FIGURE 10. -- START-UP THRESHOLD vs. TEMPERATURE
10.20
LX1562
LX1563
(VST) Start-up Threshold - (V)
13.5
(VST) Start-up Threshold
VCC = 0V to 16V CL = 1nF
10.10 10.00 9.90 9.80 9.70 9.60 9.50 9.40 -50
VCC = 0V to 16V CL = 1nF
13.0
12.5
12.0
11.5
11.0 -50
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
(TA) Ambient Temperature - (C)
(TA) Ambient Temperature - (C)
FIGURE 11. -- UV LOCKOUT HYSTERESIS vs. TEMPERATURE
6.0
FIGURE 12. -- UV LOCKOUT HYSTERESIS vs. TEMPERATURE
2.50
5.5
(VH) UV Lockout Hysteresis - (V)
LX1562
2.40 2.30 2.20 2.10 2.00 1.90 1.80 1.70 1.60
(VH) UV Lockout Hysteresis - (V)
LX1563
5.0
4.5
4.0
3.5
3.0 -50
-25
0
25
50
75
100
125
1.50 -50
-25
0
25
50
75
100
125
(TA) Ambient Temperature - (C)
(TA) Ambient Temperature - (C)
Copyright (c) 1996 Rev. 1.3 12/96
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PRODUCT DATABOOK 1996/1997
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SECOND-GENERATION POWER FACTOR C O N T R O L L E R
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D
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CHARACTERISTIC
C U RV E S
FIGURE 13. -- IDET THRESHOLD HIGH vs. TEMPERATURE
1.90 1.85
FIGURE 14. -- IDET INPUT HYSTERESIS vs. TEMPERATURE
400 350 300 250 200 150 100 50 0 -50
1.80 1.75 1.70 1.65 1.60 1.55 1.50 -50
(HD) IDET Input Hysteresis - (mV)
(VHI) IDET Threshold High - (V)
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
(TA) Ambient Temperature - (C)
(TA) Ambient Temperature - (C)
FIGURE 15. -- RUN-AWAY COMPARATOR THRESHOLD
vs. TEMPERATURE
2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 -50
FIGURE 16. -- C.S. DELAY TO OUTPUT vs. TEMPERATURE
500
(td) C.S. Delay to Output - (ns)
450 400 350
Run-Away Comp. Threshold
VCC = 12V, CL = 1nF VM1 = 1V, VEA0 = 3.7V VCS = 0V to 1.2V
300 250
200 150 -50
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
(TA) Ambient Temperature - (C)
(TA) Ambient Temperature - (C)
10
Copyright (c) 1996 Rev. 1.3 12/96
PRODUCT DATABOOK 1996/1997
LX1562/1563
SECOND-GENERATION POWER FACTOR C O N T R O L L E R
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CHARACTERISTIC
C U RV E S
FIGURE 17. -- C.S. BLANKING TIME vs. TEMPERATURE
1000
FIGURE 18. -- RESTART TIME vs. TEMPERATURE
600
(tBLK) C.S. Blanking Time - (ns)
900 800 700
500
VCC = 12V C.S. = Pulse
(tRST) Restart Time - (s)
400
300
600 500
200
400 300 -50
100
-25
0
25
50
75
100
125
0 -50
-25
0
25
50
75
100
125
(TA) Ambient Temperature - (C)
(TA) Ambient Temperature - (C)
FIGURE 19. -- FALL TIME vs. TEMPERATURE
90
FIGURE 20. -- RISE TIME vs. TEMPERATURE
200
VCC = 12V, CL = 2200pF
80 70 60
180 160
VCC = 12V CL = 2200pF
(tR) Rise Time - (ns)
-25 0 25 50 75 100 125
(tF) Fall Time - (ns)
140 120 100 80 60 40 -50
50 40
30 20 -50
-25
0
25
50
75
100
125
(TA) Ambient Temperature - (C)
(TA) Ambient Temperature - (C)
Copyright (c) 1996 Rev. 1.3 12/96
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PRODUCT DATABOOK 1996/1997
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D
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HEET
CHARACTERISTIC
C U RV E S
FIGURE 21. -- SUPPLY CURRENT vs. SUPPLY VOLTAGE
14
FIGURE 22. -- SUPPLY CURRENT vs. SUPPLY VOLTAGE
14
LX1562
12
12
LX1563
(ICC) Supply Current - (mA)
(ICC) Supply Current - (mA)
10 8
10 8
6 4
6 4
2 0 0 10 20 30 40
TA = 25C VCS = 0V VM1 = 0V VPIN2 = VPIN1
50 60
2 0 0 10 20 30 40
TA = 25C VCS = 0V VM1 = 0V VPIN2 = VPIN1
50 60
(VCC) Supply Voltage - (V)
(VCC) Supply Voltage - (V)
FIGURE 22a. -- MAXIMUM MULTIPLIER OUTPUT vs. TEMPERATURE
1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 -50
(VCLMP) Maximum Mult. Output Voltage - (V)
VCC = 12V, CL = 1nF VPIN1 = 0V, VM1 = 2V, VCS = 0-2V
-25
0
25
50
75
100
125
(TA) Ambient Temperature - (C)
12
Copyright (c) 1996 Rev. 1.3 12/96
PRODUCT DATABOOK 1996/1997
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SECOND-GENERATION POWER FACTOR C O N T R O L L E R
P
RODUCTION
D
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S
HEET
FUNCTIONAL DESCRIPTION The operation of the IC is best described by referring to the block-diagram. The output of the multiplier stage generates a voltage proportional to the product of the rectified AC line and the output of the error amplifier. This voltage serves as the reference for the inductor peak current that is sensed by the resistor in series with the external power MOSFET. When the sense voltage exceeds this threshold, C.S. comparator trips and resets the latch as well as turning the power MOSFET off. The energy stored during switch on-time is now transferred and stored in the output capacitor, causing the inductor current
Inductor Peak Current Envelope Average AC Input Current
IL
FIGURE 23 -- INDUCTOR CURRENT
TON
TOFF
to ramp down. When current reaches zero level (inductor runs out of energy) , boost diode (D1) stops conducting and the residual inductor energy and the drain to source capacitance of the power MOSFET create an LC tank circuit which causes drain voltage to resonate at this frequency. The resonating voltage is detected by the secondary winding (Idet winding) of the inductor. When this voltage swings negative "I detect" pin senses it and activates the blanking circuit , sets the latch, and turns power MOSFET on, repeating the cycle. This operation continues for the entire cycle of the AC rectified input resulting in an inductor current as shown in Figure 23. The high frequency content of this current is then filtered by the input capacitor (C1) resulting in a sine wave input current in phase with the AC line voltage. Output voltage regulation is accomplished when the error amplifier compares this voltage to an internal 2.5V reference and generates an error voltage. This voltage then controls the amplitude of the multiplier output adjusting the peak inductor current proportional to the load and line variations, maintaining a well regulated voltage.
IC DESCRIPTION UNDERVOLTAGE LOCK OUT The LX1562/63 undervoltage lock-out is designed to maintain an ultra low quiescent current of less than 300A, while guaranteeing the IC is fully functional before the output stage is activated. Comparing this to the SG3561A device, a 40% reduction in start-up current is achieved, resulting in 40% less power dissipation in the start-up resistor. This is especially important in electronic ballast applications that are designed to operate in harsh environments, with convection cooling as the only means of heat dissipation. Figure 24 shows an efficient supply voltage using the ultra low start-up current of the LX1562 in conjunction with a bootstrap winding off of the power transformer. Circuit operation is as follows: The start-up capacitor (C1) is charged by current through resistor (R1) minus the start-up current drawn by the IC. This resistor is typically chosen to provide 2X the maximum start-up current at low line to guarantee start-up under the worst case condition. Once the capacitor voltage reaches the start-up threshold, the IC turns on, starting the switching cycle. The operation of the IC demands an increase in operating current which results in discharging the capacitor. During the discharge cycle, the flyback voltage of the auxiliary winding is rectified and filtered via rectifier (D1) and charges the capacitor above the minimum operating voltage of the device and takes over as the supply voltage. The start-up capacitor and auxiliary winding must be selected such that it satisfies worst case IC conditions. Figure 25 shows start-up time and voltage of capacitor C1. Table 1 shows the start-up voltage and hysteresis for LX1562 and LX1563. The LX1562 is used for stand alone pre-regulator applications while LX1563 is ideal for applications where supply voltage is derived elsewhere and requires less than 14V start-up.
Rectified AC Line
R1
I1 > 300A IST < 300A VIN
D1
C1
LX1562
VO
GND GND
RS
FIGURE 24 -- TYPICAL APPLICATION OF START-UP CIRCUITRY
TABLE 1
Part # LX1562 LX1563 Start-Up Voltage 13.1V 9.8V Hysteresis Voltage 5.2V 2.1V
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IC DESCRIPTION VOLTAGE REFERENCE (continued)
VC1 VSTART C1 DISCHARGE
ERROR AMPLIFIER The error amplifier is an internally compensated op-amp with access to the inverting input and the output pin. The noninverting input is internally connected to the voltage reference and is not available for external connection. The amplifier is designed for an open loop gain of 80dB, along with a typical bandwidth of 1.7MHz and 49 degrees of phase margin. The boost output voltage of the power factor pre-regulator is divided down and monitored by the inverting input. Input bias current (0.5A max) can cause an output voltage error that is equal to the product of the input bias current and the value of the upper divider resistor. The amplifier's output is available for external loop compensation. Typically, the loop bandwidth is set below 10Hz in order to reject the low frequency ripple associated with 2X the line frequency. For example, if the error amplifier is configured as an integrator with 1.2Hz bandwidth, it will have 40dB ripple rejection at 120Hz frequency. This means that if the output of the error amp is allowed to have 100mV of ripple, the boost converter must be limited to less than 10V of ripple on its output. To prevent boost output run away condition that may occur during removal of the output load, a separate comparator monitors the E.A. output voltage and compares it to an internal 1.8V reference. When load is removed, E.A. output swings lower than 1.8V, trips the comparator and turns output driver off till the inverting input voltage drops below 2.5V. At this point, the E.A. output swings positive, turns the output driver back on and repeats the cycle until the load is returned to normal condition. To reduce output overshoot during line and load transients, the E.A. output is clamped to two diode drops above the reference voltage. This prohibits the amplifier from being saturated, allowing it to recover faster thus minimizing the boost voltage overshoot.
2f f = Line Freq.
VHYST
DISCHARGE TIME
BOOTSTRAP WINDING
RT & CT TIME CONSTANT
t
FIGURE 25 -- START-UP CAPACITOR VOLTAGE
VOLTAGE REFERENCE The voltage reference is a low drift bandgap design which provides a stable +2.5V output with maximum of 1.5% initial accuracy. This voltage is internally tied to the non-inverting input of the amplifier and is not available for external connection. The initial accuracy of the reference includes error amplifier input offset voltage. Figure 26 shows typical variation of the reference voltage vs. temperature.
2.52
2.51
(VR) Reference Voltage - (V)
VCC = 12V CL = 1nF
2.50 2.49
VO 1 2 R9 C4
2.48 2.47
R9
I9
1
C4
BW =
2
R10
Bias
I9 >> IBIAS
2.46
VREF
2.45 -50
1.8V
7
OUTPUT DRIVE
-25
0
25
50
75
100
125
From IDET Logic
(TA) Ambient Temperature - (C)
FIGURE 26 -- REFERENCE VOLTAGE (Including Offset) vs. TEMPERATURE
FIGURE 27 -- THE AMPLIFIER CONFIGURED AS AN INTEGRATOR FOR LOOP COMPENSATION
14
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IC DESCRIPTION MULTIPLIER The LX1562/63 features a one quadrant multiplier stage having two inputs. One (VM2) is internally driven by a DC voltage which is the difference of E.A. output and VREF. The other (VM1), is connected to an external resistor divider monitoring the rectified AC line. The output of the multiplier which is a function of both inputs, controls inductor peak current during each cycle of operation. This allows the inductor peak current to follow the AC line thus forcing the average input current to be sinusoidal. The multiplier is in the linear region if the VM1 input is limited to less than 2V and the E.A. output is kept below 3.5V under all line and load conditions. The output is internally clamped to 1.24V typically to limit the MOSFET peak current during turn on or under excessive load conditions. The equation below describes the relationship between multiplier output voltage and the its inputs. VM0 = K * VM1 * (V EA0 - VREF) where: K = Multiplier gain (typ. 0.65) VM1 = Voltage at pin3 (0 to 2V) VEA0 = Error amp output voltage (2.5 to 3.5V) VM0 = Multiplier output voltage
E.A. OUTPUT
2
for an external RC filter otherwise required for proper operation of the circuit. This function is described in detail under "current detect logic" section. The current sense comparator voltage is limited by an internal 1.24V (typ.) voltage clamp of the multiplier output. Therefore maximum switch current is typically given by: IPK (MAX) = 1.24V / RS Maximum switch peak current happens at full load and minimum line conditions.
TO PIN 7
3
Logic Circuit R
7
RS VM0
5
1sec Blank
MULT. OUTPUT
INV. 1 INPUT
VEA VREF
2.5V
VM0
FIGURE 29 -- CURRENT SENSE SECTION
VM2
CURRENT DETECT LOGIC The function of "current detect logic" is to sense the operating state of the boost inductor and to enable the output driver accordingly. To achieve this, the downward slope of the inductor current is indirectly detected by monitoring the voltage across a separate winding and connecting it to the detector input "IDET" pin. Once the inductor current reaches ground level, the voltage across the winding reverses polarity and changes the "I DET" input and the comparator output to the low state (See Figure 30). When comparator changes state, it sets the latch and turns on the output driver for a period of 1s (typ.) regardless of any changes in the latch output (Q) within this period. This ensures that if the C.S. comparator changes state due to any turn-on spike, the driver output remains on and does not turn off prematurely. However if the spike lasts longer than 1s, the output driver turns off and the MOSFET stops conducting. This type of digital current sense blanking which is not amplitude dependent has higher noise immunity than the commonly used external RC filtering, allowing for more flexibility in board layout. Since inductor voltage swings both positive and negative, internal voltage clamping is provided to protect the IC. The
VAC R1
3
VM1
4
R2
C.S. INPUT
FIGURE 28 -- MULTIPLIER SECTION
CURRENT SENSE COMPARATOR Current sense comparator is configured as a PNP input differential stage with one input internally tied to the multiplier output and the other available for current sensing. Current is converted to voltage using an external sense resistor in series with the external power MOSFET. When sense voltage exceeds the threshold set by the multiplier output, the current sense comparator terminates the gate drive to the MOSFET and resets the PWM latch. The latch insures that the output remains in a low state after the switch current falls back to zero. The LX1562/63 features a leading edge blanking circuit that eliminates the need
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IC DESCRIPTION CURRENT DETECT LOGIC (continued) upper 7.8V clamp prevents input overvoltage breakdown during switch off time, while during the on time the lower 0.7V clamp prevents substrate injection. An internal current limit resistor protects the lower clamp transistor in case the "I DET" pin is accidently shorted to ground. START-UP TIMER A start-up timer circuit eliminates the need for an external oscillator when used in stand alone applications. The timer, as shown in Figure 30, provides a means to automatically start the pre converter if the latch output Q comes up in a wrong (HI) state. The timer capacitor ramps up and resets the latch to a low state, turning the output driver on. OUTPUT DRIVER STAGE The LX1562/63 output driver is designed for direct driving of an external power MOSFET. It is a totem pole stage with 500mA peak current capability. This typically results in a 130ns rise and fall times into a 1000pF capacitive load. Additionally the output is held low during the undervoltage condition to ensure that the MOSFET remains in the off state until supply voltage reaches the start-up threshold. Internal voltage clamping ensures that output driver is always lower than 13.8V (typ.) when supply voltage variation exceeds more than rated VGS threshold (typ 20V) of the external MOSFET. This eliminates an external zener diode and extra power dissipation associated with it that otherwise is required for reliable circuit operation.
L1
HI VREF IDEF
5
OUT
7
C.S.
R
Q
300
L1 S 1.72V VTIMER C.S. Latch
1s Delay
Q
C.S.
4
C.S. VM0
FIGURE 30 -- START-UP TIMER & CURRENT DETECT LOGIC CIRCUITRY
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A P P L I C AT I O N I N F O R M A T I O N TYPICAL APPLICATION The application circuit shown in Figure 31 uses the LX1562 as the controller to implement a boost type power factor regulator. The I.C. controls the regulator, such that the inductor current is always operating in a discontinuous conduction mode with no current gaps. This mode of operation has several advantages over the fixed frequency discontinuous conduction mode: 1) The switching frequency adjusts itself to the AC line envelope, causing a sinusoidal current draw, 2) Since there is no current gap between the switching cycles, the inductor voltage does not oscillate, causing less radiated noise, 3) The lower peak inductor current causes less power dissipation in the power MOSFET.
450H 61T #22AWG 100k 1/2W L1 R3 7T D5 R4 22k 1N4935
8 VIN 5 I DET OUT 7
A set of formulas have been derived specifically for this mode, and are used throughout the design procedure. An example with the following specifications for the boost converter is given as: Input Voltage Range Output Power Efficiency Power Factor Total Harmonic Distortion 100 to 130V RMS 80W 95% at full load > 0.99 at full load < 10% at full load
followed by a step by step design procedure which walks through component selection.
VBOOST 230V
MR854 D7
D1
D3
1N4004
1N4004
AC+
EMI FILTER
R1 C1 1F 250V
LX1562
120V AC AC-
2.2M 1%
C2 22F R10 4.7M
R7
47 R5 R9 620k C5 0.1F
Q1 1RF730
3
MULT IN
D2
D4
COMP INV
2 1 4
C6 100F 400V 11k 1% R6 1.3 R8
R2
1N4004
1N4004
0.1F
29k 1%
C3 C4 .01F
GND 6
C.S.
3x 1/4W
Note: Thick trace on schematic shows high-frequency, high-current path in circuit. Lead lengths must be minimized to avoid high-frequency noise problems. FIGURE 31 -- TYPICAL APPLICATION OF THE LX1562 IN AN 80W FLUORESCENT LAMP BALLAST WITH ACTIVE POWER FACTOR CONTROL
OUTPUT VOLTAGE REQUIREMENT Since the converter is a boost type topology, it requires the output voltage to always be higher than the input voltage. It is recommended to select this voltage at least 15% higher than the maximum input voltage in order to: A) Avoid the inductor saturation during line transience, and B) To keep the operating frequency above the audible range at high line. Figure 32 (next page) shows that when boost voltage is selected near the maximum AC line, the increase in off-time could reduce the operating frequency below the audible frequency and cause inductor humming. In fact, Figure 32 (next page) shows that for 13% (100V to 130V) change in the line voltage the optimum range of the operating frequency is when off-time duty cycle (D') is between 0.57 and 0.75. This means that the boost voltage needs to be 245V when selecting D' = 0.75 at maximum AC line. In this example, D' is chosen to be 0.8, to slightly reduce the voltage rating of the back end DC to AC fluorescent lamp inverter. This sets the boost voltage at: VO = 130 * 2 = 230V 0.8
Copyright (c) 1996 Rev. 1.3 12/96
FLOURESCENT LAMP BALLAST
D6 1N4148
1M 1%
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A P P L I C AT I O N I N F O R M AT I O N OUTPUT VOLTAGE REQUIREMENT (continued) Maximum peak input current can be calculated using: 2P O = IP VP where: Converter efficiency VP Peak AC input voltage assuming: = 95%, PO = 80W, VPmin = 1002 = 141
D' =
0.05
(fn) Normalized Operating Frequency
0.2
fn = (1 - D') D'
0.15
0.1
2 VAC VO
IP =
2 x 80 = 1.2A (.95)(141)
VO f= f 4 LPO n
ILP/min AC = 2 * 1.2 = 2.4A INDUCTOR DESIGN
0.8 0.9 1.0
0.3
0.4
0.5
0.6
0.7
The inductor value is calculated assuming a 50KHz operating frequency at the nominal AC voltage using the following equation: L1 =
V O - VP VO
(D') Off Time Duty Cycle
FIGURE 32 -- NORMALIZED OPERATING FREQUENCY vs. OFF-TIME DUTY CYCLE
T VP2
4 PO
INDUCTOR PEAK CURRENT It can be shown by referring to Figure 33 that the inductor peak current is always twice the average input current. L1 =
Inductor Peak Current Envelope Average AC Input Current
where: VO VP T PO

Efficiency Output DC voltage Peak AC input voltage Switching period Output Power
.95 (
230 - 1202 230
) 20 * 10-6 * (1202)2 4 * 80
= 448H
IL
choose T = 20sec (50kHz) Figure 32 shows that at nominal AC line (D' = 0.74) the normalized frequency is 0.142 and dropping to 0.13 at maximum line condition. This translates to a 10% drop in operating frequency which is still well above the audible range. Once the inductance is known, we can either use the area product method (AP) or the Kg (based on copper losses method), for selecting proper core size. In this example, we apply the Kg approach using the following steps: Step 1: Calculate Kg using L1 ILP2 ( )2 Kg = PCU B
FIGURE 33 -- INDUCTOR CURRENT
TON
TOFF
IIN(t) = IIN =
AVE [ I
ILP 2
L
(t) ] IL 2
1 (I L) (T) = T 2
where:
IINpeak = IP = ILP
L1 B ILP PCU

Required inductance 1.724 * 10 -8 m Maximum flux density Maximum peak inductor current Maximum copper dissipation
= Inductor peak current at peak input voltage.
Assume: PCU = 1.6W (2% of total output) 2 1.724 * 10 -8 450 * 10-6 * (2.4)2 = 3.21 * 10-12 m5 Kg = 1.6 0.15
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A P P L I C AT I O N I N F O R M A T I O N INDUCTOR DESIGN (continued) Step 2: Choose a core with higher Kg than the one calculated in Step 1. A A2 Kg/core = k W E lW where: k AW AE lW Winding coefficient (typ. k=0.4) Bobbin window area Effective core area Mean length per turn MULTIPLIER COMPONENT SELECTION Calculate R1 & R2 resistor values such that under low line AC input the multiplier output is lower than the minimum clamp voltage. R2 2 VAC (MIN) * K * (V EA0 (MAX) - VREF ) < VCLAMP (MIN) R1 + R2 * where: K Mult. Gain VEA)(MAX) Maximum error amp output where multiplier is still in linear range. This voltage is 3.5V. For K = 0.65 & VCLAMP (MIN) = 1.1V, the ratio of R1/R2 is: R1 > 83 R2 Assuming R1 is selected to be: * R1 = 2.2M (1%) Step 3: Determine number of turns. N= N= L ILP B AE R2 = 2.2M = 26.4k (1%) 83 select R2 = 26.7k (1%)
Kg factor for AW AE lW Kg = 0.4
TDK PQ2625: = 47.7mm2 = 118mm2 = 56.2mm
(47.7) (118)2 (mm)5 = 4.7 * 10-12 m5 56.2
450 * 10-6 * 2.4 = 61 turns 0.15 * 118 * 10-6 AW 47.7 AWIRE = k = 0.4 = 0.31mm2 N 61 = 480mil2 choose #22 AWG with r = 0.0165/feet resistance. RW = N * lw * r RW = 0.185 Step 4: Calculate air gap. O N2 AE lg = L 4 * 10-7 * (61) 2 * 118 * 10-6 lq = 450 * 10-6 CURRENT SENSE RESISTOR Current sense resistor, R6 is selected using the minimum multiplier output clamp voltage and the maximum inductor peak current such that: VCLAMP(MIN) 1.1 R6 = = = 0.45 IL (MAX) 2.4 Power dissipation is approximated by: PR PR 2 VAC(MIN) 1I 2 (1 - D'MIN), where D'MIN= 1 6 2 (MAX) VBOOST 1 (2.4)2 (1 - 0.61) = 0.374 6
* For high input applications such as 277V, R1 must be divided into two resistors in series to meet the maximum rated voltage of the resistors. To improve THD further (typ. 2-3%), a high value resistor can be connected from the supply voltage to this pin to allow an increase in the switch on-time at the zero crossing by adding an effective offset at the multiplier output. ERROR AMPLIFIER COMPONENT SELECTION Boost voltage is programmed with R7 & R8 resistor dividers using the following equation: R7 R8 = VBOOST VREF -1,
= 0.122cm = 48 mil
assuming that the product of R7 and the E.A. input bias current does not cause significant error in the output voltage setting. Assuming R7 = 1M (for output voltage of higher than 250V,
two resistors may be added in series to meet the voltage requirement of the resistor.)
VERROR (106) (0.5 * 10-6) = 0.5V, Calculating R8: R8 = R7
VBOOST VREF
which is < 0.25% of the output voltage.
= 11k (1%) -1
Select THREE 1.3, 1/4W carbon comp resistors in parallel.
Worst case output tolerance is the total of 3.75% which is the sum of 1.5% (Ref), 2% (resistor dividers), and 0.25% (E.A. input bias current).
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A P P L I C AT I O N I N F O R M AT I O N ERROR AMPLIFIER COMPONENT SELECTION (continued) Capacitor C5 is primarily selected to reject the output ripple associated with twice the line frequency. For a 40dB ripple rejection: 100 C5 where fl = 2x line frequency 2 fl R7 C5 100 = 0.062F, 2 * 120 * 2.2 * 106 Select C5 = 0.1F R3 < SUPPLY VOLTAGE Resistor R3 must be selected such that it ensures converter startup at low line and is rated for high line power dissipation. R3 < 2 VAC (MIN) IST (MAX) where: I ST Maximum start-up current Start-up voltage VST T ST(MAX) Maximum start-up time at AC power-on
Resistor R9 can be used to improve load transient response at the cost of loosing 1 or 2% of load regulation. The value of this resistor should be much greater than R8: R9 = 620k One way of achieving desired load transient response without resorting to a complex mathematical model of the converter, is to dynamically switch the output load and empirically find the compensation network. The value of resistor R9 is selected using the method shown in Figure 34.
VBOOST Min. Load RL
2 * 100 = 466k 0.3 * 10 -3
R3 > 4 VAC (MAX) R3 > 68k ,
(to keep power dissipation below 0.5W)
select R3 = 120k.
Start-up time of converter is given by: T ST (MAX) C2
2 VAC (MIN) - IST R3
VST
for our application this will be 25ms/F. The start-up capacitor is selected such that capacitor discharge time is always longer than the time it takes for the bootstrap voltage to reach above the minimum start-up threshold of the IC.
10Hz 50% D.C.
C3 <
IOP * t VMIN
where: IOP
FIGURE 34 -- LOAD TRANSIENT RESPONSE CIRCUIT
IDETECT COMPONENT SELECTION Figure 35 shows voltage envelope generated by flyback voltage across IDET winding: Select turns ratio n such that, n= 5V VBOOST - 2 VAC (MAX) 5V = 0.11
nVAC n (VBOOST - VAC)
Maximum dynamic supply current of the IC t Rise time of the bootstrap voltage VMIN Minimum hysteresis voltage (4V for 1562,
1.7V for 1563)
10 * 10-3 * 10 * 10-3 C3 < 4 Select C3 = 33F.
= 29F
Start-up time is approximately 0.8 seconds. The auxiliary winding turns are selected such that it provides 15V of operating voltage.
FIGURE 35 -- FLYBACK VOLTAGE ACROSS IDET WINDING
n=
230 - 2 * 130 IDET winding turns are selected to be 7T. and R4 resistor: n * VBOOST 3 * 10-3 0.11 * 230 3 * 10-3
NS NP *
VS VO
= 61 *
VS VO
= 4T
< R4 < 500k < R4 < 500k, or 8.4k < R4 < 500k
However, in this example IDETECT winding is used to power the IC which eliminates the need for a third winding. This is possible since the internal clamping of the output drive limits the gate drive voltage to 14V (typ.) if the supply voltage exceeds this limit.
Select R4 = 22k
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A P P L I C AT I O N I N F O R M A T I O N POWER MOSFET SELECTION The voltage rating of MOSFET and rectifier must be higher than the maximum value of the output voltage. VDS 1.2 VO MAX VDS 282V Assuming is the percentage of allowable input current ripple, C1 can be calculated using the following equations: REFF = C1 if = 3% REFF = C1
D
2 PO IP2 1 2 REFF fSW fSW Switching frequency of inductor current at peak input voltage.
The RMS current can be approximated by multiplying the RMS current at the peak of the line by 0.7. IRMS = 0.7 ILP D/3 D On-time duty cycle
ILP
D = 0.39 at VAC = 100V ILP = 2.4A IRMS = (0.7)(2.4)(.39/3) = 0.61A PDC RDS IRMS2 PDC allowable power dissipation. 1 = 1.6 RDS 0.61
2 x 80 (.95)(1.2)2 1
= 117
(.03)(2)(117)(50000)
= 0.9F
IRMS/triangle = ILP D/3
choose 1F, 250V capacitor. OUTPUT CAPACITOR SELECTION There are mainly two criteria for selecting the output capacitor: A large enough capacitance to maintain a low ripple voltage, and a low ESR value in order to prevent high power dissipation due to RMS currents. The output capacitance can be approximated from the following equation: C6 IDC 2 fLINE V 80 230 = 0.348A where: IDC DC output current DV Output ripple
IRF730 with RDS = 1 and VDS = 400V meets the above requirements. INPUT RECTIFIER AND CAPACITOR SELECTION The current through each diode is a half-wave rectified sine wave. The maximum current happens at minimum line with a peak value of 1.2A. IPEAK 1.2 IAVE = = = 0.38A choose 1N4004 with 1A rating. PDISS = (IAVE) (VF) = 0.38 x 0.9 = 0.344W TJ = TA + PD x JA assuming JA = 65C/W for 1/8" lead length.
IDC =
assuming 5% peak to peak ripple, 0.348 C6 = 81F 2 (60) (11.5) choose C6 = 100F.
TJ = 80 + (.344)(65) = 102C
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T Y P I C A L A P P L I C AT I O N S
120V
L1 R3 D1 D3 450H 61T #22AWG #26AWG R4
8 VIN 5 IDET
D7
VBOOST
7T D5
AC+ 120V AC AC-
R1 C1
C2 R10
D6 R5
R7
LX1562
OUT 7
Q1
R9
COMP 2
C6
3
MULT IN
R2 D2 D4 C4
C3
INV 1 C.S. 4
C5
R8 R6
GND 6
Note: Thick trace on schematic shows high-frequency, high-current path in circuit. Lead lengths must be minimized to avoid high-frequency noise problems. FIGURE 36 -- TYPICAL APPLICATION OF THE LX1562 IN AN 80W FLUORESCENT LAMP BALLAST WITH ACTIVE POWER FACTOR CONTROL.
Electrical 120VAC Input -- 230VDC / 80W Output Specification Ref. Component Ref. Component Manuf. IC L1 Q1 D1-D4 D5 D6 D7 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 LX1562 PQ2625/H7C1 Core IRF730, 400V, 1 rds IN4004 1A, 400V 1N4935 1A 1N4148 (improves Q1 power dissipation) MR854, 3A, 400V 2.2M, 1% 26.7k, 1% 100k, 1/2W 22k 47 1.5, Carbon type (3X) 1M, 1% 11k, 1% 620k (improves load transient response) 4.7M Linfinity TDK I.R. Motorola Motorola Motorola Motorola C1 C2 C3 C4 C5 C6 QXF2E105KRPT 1F/250V - Plastic Film (high freq.) 22F/35V - Electrolytic 0.1F/50V - Ceramic 0.01F/50V - Ceramic 0.1F/50V - Ceramic LGQ2G101MHS A/Z* 100F/400V - Electrolytic * A = 25mm diam. Z = 22mm diam.
Manuf.
Nichicon
Nichicon
A complete evaluation board is available from Linfinity Microelectronics Inc.
22
FLOURESCENT LAMP BALLAST
Copyright (c) 1996 Rev. 1.3 12/96
PRODUCT DATABOOK 1996/1997
LX1562/1563
SECOND-GENERATION POWER FACTOR C O N T R O L L E R
P
RODUCTION
D
ATA
S
HEET
T Y P I C A L A P P L I C AT I O N S
80T
L1 1.2mH
220V
#24AWG #26AWG #26AWG
D7 R4
VBOOST
R3 D1 D3
7T 4T
D5
8 5 IDET
AC+ 220V AC AC-
D6 R5
R7
R1 C1
C2 R10
VIN
LX1562
OUT 7
Q1
R9
COMP 2
C6
3
MULT IN
R2 D2 D4 C4
C3
GND 6
INV 1 4 C.S.
C5
R8 R6
Note: Thick trace on schematic shows high-frequency, high-current path in circuit. Lead lengths must be minimized to avoid high-frequency noise problems. FIGURE 37 -- TYPICAL APPLICATION OF THE LX1562 IN AN 80W FLUORESCENT LAMP BALLAST WITH ACTIVE POWER FACTOR CONTROL.
Electrical 220VAC Input -- 400VDC / 80W Output Specification Ref. Component Ref. Component Manuf. IC L1 Q1 D1-D4 D5 D6 D7 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 LX1562 PQ2625/H7C1 Core IRF830, 500V, 1.5 rds IN4007 1A, 1000V 1N4935 1A 1N4148 (improves Q1 power dissipation) MR856, 3A, 600V 2.2M, 1% 12k, 1% 220k, 1/2W 22k 47 1.8, Carbon type (2X) 1M, 1% 6.19k, 1% 620k (improves load transient response) 2.7M Linfinity TDK I.R. Motorola Motorola Motorola Motorola C1 C2 C3 C4 C5 C6* QXF2J224KRPT 0.22F/630V - Plastic Film 22F/35V - Electrolytic 0.1F/50V - Ceramic 0.01F/50V - Ceramic 0.1F/50V - Ceramic LGQ2W680MHS A/Z* 68F/450V - Electrolytic * A = 25mm diam. Z = 22mm diam.
Manuf.
Nichicon
Nichicon
A complete evaluation board is available from Linfinity Microelectronics Inc.
Copyright (c) 1996 Rev. 1.3 12/96
FLOURESCENT LAMP BALLAST
23
PRODUCT DATABOOK 1996/1997
LX1562/1563
SECOND-GENERATION POWER FACTOR C O N T R O L L E R
P
RODUCTION
D
ATA
S
HEET
T Y P I C A L A P P L I C AT I O N S
80T
L1 2.2mH
277V
#24AWG #26AWG #26AWG
D7 R4
VBOOST
R3 D1 D3
15T 3T
D5
8 5 IDET
AC+ 277V AC AC-
D6 R5
R7A R7B
Q1
R1 C1
C2 R10
VIN
LX1562
OUT 7
R9
COMP INV 2 1 4
C6A C6B
3
MULT IN
R2 D2 D4 C4
C3
C5
R8 R6
GND 6
C.S.
Note: Thick trace on schematic shows high-frequency, high-current path in circuit. Lead lengths must be minimized to avoid high-frequency noise problems. FIGURE 38 -- TYPICAL APPLICATION OF THE LX1562 IN AN 80W FLUORESCENT LAMP BALLAST WITH ACTIVE POWER FACTOR CONTROL.
Electrical 277VAC Input -- 480VDC / 80W Output Specification Ref. Component Ref. Component Manuf. IC L1 Q1 D1-D4 D5 D6 D7 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 LX1562 PQ2625/H7C1 Core IRF830, 500V, 1.5 rds IN4007 1A, 1000V 1N4935 1A 1N4148 (improves Q1 power dissipation) MR856, 3A, 600V 2.2M, 1% 10k, 1% 390k, 1/2W 22k 47 2.2, Carbon type (2X) 499k, 1% (2X) 5.23k, 1% 620k (improves load transient response) 2.2M Linfinity TDK I.R. Motorola Motorola Motorola Motorola C1 C2 C3 C4 C5 C6 QXF2J224KRPT 0.22F/630V - Plastic Film 22F/35V - Electrolytic 0.1F/50V - Ceramic 0.01F/50V - Ceramic 0.22F/50V - Ceramic UVZ2F470MEH (2X) 47F/315V - Electrolytic
Manuf.
Nichicon
Nichicon
A complete evaluation board is available from Linfinity Microelectronics Inc.
24
FLOURESCENT LAMP BALLAST
Copyright (c) 1996 Rev. 1.3 12/96
PRODUCT DATABOOK 1996/1997
LX1562/1563
SECOND-GENERATION POWER FACTOR C O N T R O L L E R
P
RODUCTION
D
ATA
S
HEET
T Y P I C A L A P P L I C AT I O N S
62T
L1 450H
90V - 265V
#24AWG #26AWG #26AWG
D7 R4
VBOOST
R3 D1 D3
7T 3T
D5
8 5 IDET
AC+ 90-265V AC AC-
D6 R5
R7
R1 C1
C2
VIN
LX1562
OUT 7
Q1
R9
COMP 2
C6
3
MULT IN
R2 D2 D4 C4
C3
GND 6
INV 1 4 C.S.
C5
R8 R6
Note: Thick trace on schematic shows high-frequency, high-current path in circuit. Lead lengths must be minimized to avoid high-frequency noise problems. FIGURE 39 -- TYPICAL APPLICATION OF THE LX1562 IN AN 80W FLUORESCENT LAMP BALLAST WITH ACTIVE POWER FACTOR CONTROL.
Electrical 90-265VAC Input -- 400VDC / 80W Output Specification Ref. Component Ref. Component Manuf. IC L1 Q1 D1-D4 D5 D6 D7 R1 R2 R3 R4 R5 R6 R7 R8 R9 LX1562 PQ2625/H7C1 Core IRF840, 500V, 1 rds IN4007 1A, 1000V 1N4935 1A 1N4148 (improves Q1 power dissipation) MR856, 3A, 600V 2.2M, 1% 16.3k, 1% 130k, 1/2W 22k 47 1, Carbon type (4X) 1M, 1% 6.19k, 1% 620k (improves load transient response) Linfinity TDK I.R. Motorola Motorola Motorola Motorola C1 C2 C3 C4 C5 C6* QXF2J224KRPT 0.47F/630V - Plastic Film 22F/35V - Electrolytic 0.1F/50V - Ceramic 0.01F/50V - Ceramic 0.33F/50V - Ceramic LGQ2W680MHS A/Z* 68F/450V - Electrolytic * A = 25mm diam. Z = 22mm diam.
Manuf.
Nichicon
Nichicon
A complete evaluation board is available from Linfinity Microelectronics Inc.
Copyright (c) 1996 Rev. 1.3 12/96
FLOURESCENT LAMP BALLAST
25

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